Low Power Data Bus Encoding & Decoding Schemes

With shrinking feature size and increasing frequency, power dissipation on data bus has become the most predominant factor than the power dissipation in other parts of the circuitry. The large intrinsic capacitance associated with buses is responsible for a substantial fraction (approx 40%) of total power dissipated, because the bus power dissipation is proportional to switching activity. The main disadvantage of the existing power aware encoding schemes such as Bus Invert and Bus Invert Transition Signaling is the extra bus line used to indicate the receiver that the data is encoded or uncoded. A methodology has been proposed in this project to get rid of this extra bus line. To support this claim, detailed implementation of such additional logic is presented. A logical model of data buses is presented and a family of techniques is proposed that can reduce average power consumption of the bus by 34% With new implemented technique defined, we present technique for the synthesis of encoding and decoding interface logic that minimizes the average number of transitions on heavily-loaded global bus lines at no cost in communication throughput . The distinguishing feature of our approach is that it does not rely on designer’s intuition, but it automatically constructs low-transition activity codes and hardware implementation of encoders and decoders, given information onward-level statistics. We propose an accurate method that is applicable to low-width buses, as well as approximate methods that scale well with bus width.